Hereinafter, a description is given with reference to FIGS. 1 and 2. Like element numerals are used to denote like elements in FIGS. 1 and 2.
FIG. 1 shows an image of use of a semiconductor memory by a user and the basic configuration of a semiconductor memory. A semiconductor memory, in particular, a non-volatile memory, is used as non-volatile storage means for an audio player 2 being carried by a user 1, a digital camera, or the like. For example, the audio player 2 contains a semiconductor integrated circuit 3 including a non-volatile memory for storing music data or the like. The semiconductor integrated circuit 3 is constituted by a combination of a plurality of transistors 4.
The transistors 4 are fabricated on a single crystal semiconductor substrate or a single crystal semiconductor thin film on an insulator. The transistors 4 are constituted by memory cells such as a plurality of field effect transistors (FET, hereinafter, simply referred to as transistors).
The basic configuration of the transistor 4 is as follows. A source electrode 102 and a drain electrode 103 are provided on a semiconductor substrate 101 (silicon material). An insulation film 105 is formed on the source electrode 102 and the drain electrode 103. A layer 107 composed of a certain semiconductor material is formed on the insulation film 105. An insulation film 108 is formed on the layer 107. A gate electrode 104 is formed on the insulation film 108. Side walls 106 are further formed on the insulation film 105 to sandwich the layer 107 composed of a certain semiconductor material, the insulation film 108, and the gate electrode 104. These components are integrated to constitute the transistor 4.
Conventionally, higher speed and higher packing density of the semiconductor integrated circuit 3 have been achieved by reducing the size of the transistors 4. This results in larger storage capacity per unit area and the like and hence more advanced information processing has been achieved.
However, such a reduction in size has physical limits and it will be difficult to substantially provide higher performance by simply reducing the size of the transistors 4. In particular, when a fabrication process is conducted at an accuracy on the order of nanometers, the limits become obvious.
With the recent trend toward higher performance in information communications equipment, non-volatile memories capable of storing data without receiving power have become widely used and there is an increasing demand for higher storage capacity for such memories. There is also a demand for higher input/output speed of the memory for the purpose of handling a large data stream (moving image data or the like).
Products using semiconductor memories such as the audio player 2 have high competitiveness because large data can be input and output at high speed in spite of the small size of the products.
To overcome the above-described problem, that is, to store more data per unit area and to update a memory at high speed, a technique of multi-valuing a memory device has been developed. However, in conventional multi-valuing techniques, there is a trade-off between a decrease in time for which electrons are injected and an increase in time for which charges are retained, that is, between the reading/writing speed of a memory and memory retention time. For this reason, it is difficult to provide a high-performance memory device having both a large capacity and high input/output speed, which has been a problem.
To overcome this problem, a technique has been disclosed in which the layer 107 composed of a certain semiconductor material is constituted by a floating gate (Japanese Unexamined Patent Application Publication No. 09-260611). Hereinafter, a conventional floating gate structure is described with reference to FIG. 2. FIG. 2 is a section view of a conventional semiconductor memory having a floating gate.
A floating gate 200 is constituted by a laminate of a plurality of nodes. Each node has a configuration where a plurality of quantum dots composed of a certain material are covered with an insulation film composed of a certain material. These nodes can be categorized on the basis of function into a control node for controlling injection and emission of electrons and a charge accumulation node for accumulating electrons.
The floating gate 200 described in Japanese Unexamined Patent Application Publication No. 09-260611 is constituted by a laminate of a control node 210 and a charge accumulation node 220. The control node 210 and the charge accumulation node 220 are constituted by silicon quantum dots of the same type and insulation films of the same type. A plurality of silicon quantum dots in the control node 210 are regularly arranged to correspond to one unit of silicon quantum dots in the charge accumulation node 220.
According to this technique, the threshold voltage of a transistor is controlled by injecting electrons into silicon quantum dots, thereby making the transistor function as a multivalued memory. Use of such a transistor permits expression of multiple values such as 0, 1, 2, and 3, which is different from conventional memory operations using binary values of 0 and 1. As a result, the storage capacity of a memory can be increased while the area of possession in the device remains the same and this memory can also achieve a certain level of input/output speed.